1. Field of the Invention
The present invention relates to a three-dimensional (3D) integrated circuit (IC), and more particularly, to a 3D IC using a through silicon via (TSV) and a method of repairing TSVs of the 3D IC.
2. Discussion of Related Art
Recently, as electronic products have been developed to have a high capacity and a high density and to be lighter, operating voltages and sizes of electronic devices have been decreased. The existing two-dimensional (2D) mounting methods have problems, for example, that signals are transmitted at low speeds and a packaging area increases due to a large number of input/output (I/O) pads, and are thus not in accord with a current tendency of the industry of electronic products. Thus, research has been actively conducted on three-dimensional (3D) packaging methods of mounting integrated circuits (ICs) by stacking them in a vertical direction. Among the 3D packaging methods, most attention has been paid to a through silicon via (TSV) technique of forming through-holes in a silicon wafer and using the through-holes as electrical paths.
In general, when a TSV has a defect, a redundant TSV is used to repair the TSV with the defect. When a number of redundant TSVs is provided to be in proportional to the number of TSVs that are actually included in a 3D IC, a rate of successfully repairing failed TSVs is high.
However, redundant TSVs are large in size and thus there is a limit to arranging a large number of redundant TSVs in a 3D IC.
When a process of arranging a large number of redundant TSVs in a 3D IC is performed, the process is difficult to be performed and may thus cause a defect to occur in the 3D IC. This is because the process of arranging a large number of redundant TSVs in a 3D IC may cause layers in the vicinity of the redundant TSVs to deform, and redundant TSVs may be influenced by a process of arranging layers in the vicinity of the redundant TSVs.
Also, manufacturing costs are high when a large number of redundant TSVs are arranged to repair failed TSVs.